The present invention relates to a method for selective deposition of Silicon (Si) or Silicon Germanium (SiGe) on a Si or SiGe surface. The invention further relates to a method for differential metal silicide formation, and to a method for forming a CMOS semiconductor device with an NMOS field effect transistor, which has elevated source and drain regions, and with a PMOS field effect transistor, which has non-elevated source and drain regions.
Semiconductor processing flows employ photolithography steps for patterning the Silicon wafer. For instance, in CMOS (complementary metal oxide semiconductor) technology, PMOS- and NMOS-specific processing steps like, e.g., specific implantations or epitaxial and non-epitaxial Si or SiGe deposition are performed using photolithography in order to provide the required selectivity of processing.
A typical example of a selective growth method for Silicon that makes use of photolithography processing is presented in U.S. Pat. No. 6,696,328 B2. In order to selectively grow a second polysilicon layer on an exposed first polysilicon layer only in an NMOS region, but not in a PMOS region, the top of the PMOS region is covered by a hard mask layer. This way, the second polysilicon layer is only deposited in the NMOS region. The hard mask is also used to protect the PMOS region during subsequent ion implantation into the NMOS region for N-type doping.
Photolithography involves a combination of substrate preparation, photoresist application, soft-baking, exposure, developing, hard-baking, etching, and various other chemical treatments (thinning agents, edge-bead removal etc.) in repeated steps. Therefore, due to the complex processing sequence with high resolution and extreme accuracy requirements, photolithography represent a very high cost factor in semiconductor processing.
It is preferred to provide a method for selective deposition of Si or SiGe on a Si or SiGe surface that reduces the processing cost by reducing the use of photolithography.